Use a junction field-effect transistor common-source gain stage with a drain resistor between 3.3 kΩ and 10 kΩ and a source resistor near 470 Ω–1.5 kΩ to obtain voltage gain suitable for small audio or sensor signals. A typical configuration places the signal input through a 100 nF–1 µF coupling capacitor to the gate, while the gate itself remains referenced to ground through a resistor around 1 MΩ. This arrangement stabilizes the operating point while maintaining extremely high input resistance, often exceeding 10 MΩ.
The active device works in depletion mode, so correct biasing relies on the voltage drop across the source resistor. With a supply between 9 V and 15 V, many small-signal transistors such as the classic junction field-effect type reach a quiescent drain current near 2–5 mA. When the drain load equals about 4.7 kΩ, voltage gain frequently falls within 5–20×, depending on the device transconductance. A bypass capacitor across the source resistor, typically 22 µF–100 µF, raises gain by reducing AC degeneration.
Signal output is usually taken from the drain through another coupling capacitor around 1 µF–10 µF, feeding the next stage or measurement input. The drain node should sit roughly at 40–60 % of the supply voltage for symmetrical signal swing. Adjusting the source resistor slightly upward or downward shifts this operating point. Small variations of only 100–200 Ω can noticeably change linearity and distortion.
For stable operation on a breadboard or compact PCB, keep the gate lead short and place a 100 nF supply decoupling capacitor close to the transistor. Shielded cable for the input path reduces interference pickup. With these component values and layout choices, the transistor stage produces low-noise voltage gain suitable for microphones, guitar pickups, and high-impedance sensor probes.
Field-Effect Gain Stage Layout: Practical Design and Analysis
Select a depletion-mode field transistor with drain current rating near 5–15 mA and transconductance above 2 mS to achieve stable small-signal voltage gain in low-noise stages. Bias the gate near 0 V through a resistor between 470 kΩ and 2.2 MΩ while the source uses a self-bias resistor typically from 220 Ω to 1.5 kΩ. Supply rails between 9 V and 24 V allow adequate headroom. Drain load values around 3.3 kΩ–10 kΩ commonly produce voltage multiplication from 8× to 25× depending on device parameters and quiescent current.
Stable operating point calculation depends on drain current and pinch-off voltage. Measure or obtain the following device parameters before choosing resistor values.
- Pinch-off voltage: usually −0.5 V to −6 V depending on model
- Maximum drain current at zero gate bias: often 2 mA–20 mA
- Transconductance slope around the chosen bias point
Example target: quiescent drain current ≈ 4 mA with a 12 V supply. With a 4.7 kΩ drain resistor, the voltage drop becomes about 18.8 V at 4 mA, so reduce current to ~2 mA or select a smaller load such as 2.2 kΩ to maintain midpoint drain potential.
Signal coupling requires capacitors sized by the desired low-frequency cutoff. Calculate reactance so it stays far below the surrounding resistance. Practical component ranges:
- Input coupling capacitor: 100 nF–470 nF for sources near 10 kΩ
- Output coupling capacitor: 1 µF–10 µF when feeding loads above 10 kΩ
- Source bypass capacitor: 22 µF–220 µF to increase AC gain
Without source bypassing, voltage gain typically falls by 40–70 % but linearity improves.
Assembly layout strongly affects noise and stability. Keep the gate lead short, place the bias resistor directly at the gate pin, and route the supply line separately from input traces. Recommended practices:
- Star-ground the input return and source resistor.
- Position the drain load away from the gate node.
- Add a 100 nF decoupling capacitor between supply and ground within 1–2 cm of the transistor.
- Shield the input wire if source impedance exceeds 50 kΩ.
Verification requires measuring three voltages: gate, source, and drain. Typical readings during correct biasing show gate ≈0 V, source between 0.3 V and 2 V depending on resistor choice, and drain near half of the supply potential. If the drain voltage approaches the supply rail, reduce the drain resistor or increase source resistance; if it falls near ground, raise the drain resistor or lower source resistance. Small adjustments of 10–20 % usually place the device into the desired linear region for clean signal magnification.